The Institute of Electronics Engineers of the Philippines (IECEP), Inc. is sponsoring a seminarworkshop on Field Programmable Gate Array. The course will be credited with equivalent CPE units.

Description
This 15-hours seminar-workshop covers digital design using CPLD/FPGA with hardware programming language -- VERILOG.

Objectives
To understand the hardware programming languages— VERILOG
To have a hands-on knowledge of VERILOG and their application using the CPLD/FPGA Development Kit
To understand Digital design better through the use of CPLD/FPGA and HDL

Topics
Introduction to hardware programming language (VERILOG)
Behavioral modeling using HDL
Sequential processing using HDL
HDL synthesis
HDL Case Studies and Applications

Prerequisite
Digital Design Course

Outline:

Session 1
Introduction to the Workshop
CPLD/FPGA and Verilog information
Verilog Modeling
--- Top down modeling
--- Sample design
Lexical Conventions
Module anatomy
Port declarations
Module instances
Data types
--- Nets
--- Registers
Parameters
Procedural blocks
Timing controls
Time and event queues
Blocking Procedural assignments
Non-blocking Procedural assignments
Operators

Session 2
Introduction to ModelSim
Introduction to Altera Quartus Program
Exercises on using ModelSim and Quartus

Session 3
Programming statements
Sensitivity lists
Continuous assignments
Primitives
User defined tasks
User defined functions
Timing accuracy
Tri-state buses & bidirectional ports
Finite State machines
--- Implicit
--- Explicit
--- One-hot
--- FSM Exercise

Session 4
Introduction to CPLD/FPGA Development Kit
Sample Exercises using CPLD/FPGA Development Kit

Session 5
Case Studies and Design Techniques
Exercises using CPLD/FPGA Development Kit